1. Field of the Invention
The present invention generally relates to drivers for driving a liquid crystal display, and more particularly to a gate driver for scanning a gate line of a liquid crystal display and a data driver for driving a data line of the liquid crystal display based on display data.
2. Description of the Related Art
In a liquid crystal display (LCD), dots including transistors are provided in the horizontal and vertical directions thereof. Gate lines extending in the horizontal direction are connected to gates of the transistors of the individual dots, and data lines extending in the vertical direction are connected to capacitors of the individual dots via the transistors. When data are displayed on the liquid crystal display, a gate driver sequentially drives an individual gate line so that transistors in the gate line can be charged with electricity. Data from a data driver whose amount corresponds to one horizontal line of the liquid crystal display are simultaneously written in individual dots in the gate line via the transistors charged with electricity.
FIG. 1 shows a structure of a conventional liquid crystal display.
The liquid crystal display in FIG. 1 comprises an LCD panel 10, a timing controller 11, a plurality of gate drivers 12, and a plurality of data drivers 13. Dots including transistors, which are not illustrated in FIG. 1, are provided in the horizontal and vertical directions of the LCD panel 10. Gate lines extending in the horizontal direction from the gate driver 12 are connected to gates of transistors of individual dots, and data lines extending in the vertical direction from the data driver 13 are connected to capacitors of the individual dots via the transistors.
The timing controller 11 receives a clock signal CK, display data IXX, and a display enable signal ENAB for indicating timing with respect to a display position via an interface I/F. The timing controller 11 counts clock pulses of the clock signal CK since the display enable signal ENAB becomes ON in order to determine timing with respect to a horizontal position and generate various control signals. Furthermore, the timing controller 11 examines the number of the display enable signals ENAB to determine timing with respect to a vertical position and generate various control signals. Additionally, the timing controller 11 can detect a position of the head of each frame by finding a position where the display enable signal ENAB remains LOW during more than a predetermined number of clock pulses.
The control signal supplied to the gate driver 12 by the timing controller 11 contains a gate clock signal GCLK, a gate start signal GST, and a gate output enable signal GOE. The gate clock signal GCLK is a synchronizing signal for sequentially shifting individual gate lines driven synchronously with the rising edge of the gate clock signal GCLK. Additionally, the gate clock signal GCLK also serves as a synchronizing signal for sequentially shifting individual transistors included in a gate line being ON gates in the vertical direction synchronously with the rising edge of the gate clock signal GCLK. The gate start signal GST is a synchronizing signal for designating timing when the head of gate lines is switched ON, that is, the timing corresponding to the start timing of a frame. The gate output enable signal GOE is a signal for designating to make all gate lines non-driven by switching the above-mentioned operation.
A control signal supplied to the data driver 13 by the timing controller 11 contains a dot clock signal DCK, a data start signal DST, a latch pulse LP, and a polarity signal POL. The dot clock signal DCK is a clock pulse for fetching display data DXX in a register synchronously with the rising edge of the dot clock signal DCK. The data start signal DST is a signal for designating a start position of the display data DXX that the data driver 13 is responsible to display. Timing of the data start signal DST is set as the start point, and the display data DXX corresponding to an individual dot is sequentially fetched in the register in accordance with the dot clock signal DCK. The latch pulse LP is a signal for latching the display data DXX sequentially fetched in the register to an internal latch. The latched display data signal is transmitted to a DA converter. Then, the DA converter converts the transmitted display data signal into an analog gradation signal, and the converted analog gradation signal is supplied to the LCD panel 10 as a data line driving signal. The polarity signal POL is a signal supplied to the DA converter and designates an output polarity of each data line. In order to prevent characteristic deterioration of the liquid crystal of the liquid crystal display, it is necessary to periodically inverse the output polarity of the individual data line. Accordingly, the polarity signal POL is used to determine the output polarity of the data line for a common voltage.
When these control signals are deteriorated under the influence of noise, there is a probability that the deterioration causes a crucial improper operation of the liquid crystal display. Thus, with respect to wirings for the control signals, it is necessary to care for crosstalk between the wirings and mount the wirings for the control signals without congestion. However, the comparatively large number of the control signal cables compels the wiring board thereof to have a large area and consequently adversely affects the cost reduction. Thus, it is desired to minimize the number of control signals supplied to the individual drivers insofar as the current control functions are maintained.
Besides the above-mentioned problem on the control signals, there is a similar problem on the display data. A recent liquid crystal display is designed to increase the number of data lines driven by data drivers thereof. Namely, the recent liquid crystal display is formed so as to receive two types of display data with respect to an even dot and an odd dot in order to achieve the high fineness and the high quality display. In this structure, it is possible to finely display the display data, and at the same time to set the transmission speed of the display data at the speed to which devices therein can normally react. For instance, when the transmission path is divided into the two types, it is possible to reduce the transmission frequency to ½.
The display data are required to have the number of signals corresponding to bits for the number of the display gradation because the display data have the separate number of signals for individual RGB components. For instance, when 8 bits (256 gradations) are prepared to display a color image, it is necessary to prepare 8 (bits)×3 (3 colors for the RGB)×2 (even and odd dots)=48 signal lines. When the large number of signal lines is mounted, the liquid crystal display is forced to have a large wiring substrate. Then arises the problem of the increasing cost for parts used in the liquid crystal display.